The present invention relates generally to integrated semiconductor digital circuits, and more particularly to regulation of signal propagation delay presented by individual ones of a number of electronic circuits formed on an integrated circuit chip.
It is well known that the speed of electronic circuits (i.e., the propagation delay exhibited by a gate of an electronic digital circuit) formed on a semiconductor circuit chip can vary from chip to chip due to process variations. Typically, such gate delays can vary as much as 30% from chip to chip, and must be taken into account by designers. For example, a designer must be aware of the fact that when his or her design is fabricated in integrated circuit form, one particular chip may operate faster (have smaller gate delays) or slower (have greater gate delays) than another identical chip. The designer must be aware of the maximum and minimum limits of gate delay variations, and take them into account to make sure that digital signals converge at the inputs of any particular digital gate when they should, and/or remain long enough to be acted upon.
Of course, circuit manufacturers can tighten their specifications to reduce process variations experienced during integrated circuits fabrication. However, this solution can be very expensive. Accordingly, a happy medium is reached between a circuit speed variation that can be tolerated and fabrication expense. The result: Speed of the circuitry is reduced; good circuit design practice requires that the circuits of the chip be designed with operating speeds at the lower end of the variation range--even if not always true on an individual chip basis.
There have been techniques proposed that provide dynamic regulation of an electronic circuit's delay. These techniques, however, are generally limited to controlling small circuit operating parameters in the internal switching and amplifying sections of the gate. It has been found, however, that process variations, insofar as gate delays are concerned, often affect the output stages of a gate. This is because a digital gate typically drives a number of other gates, and must, therefore, be capable of sourcing (or sinking) relatively large output currents during output transitions. Process variations can cause concomitant variations in the impedance (primarily capacitance) seen by these output stages which affect the time it takes for the gate's output to change from one state to another.